1. Field of the Invention
The invention relates to a semiconductor device and a preparing method therefor and more particularly to a NOR-type mask ROM (Read Only Memory) provided with a memory cell function memorizing 2 bit information and a preparing method for the NOR-type mask ROM.
2. Description of the Related Art
A conventional NOR-type mask ROM (provided by previously forming source/drain regions followed by formation of gate electrodes) is exemplified in FIGS. 6 (a), 6 (b) and 6 (c). The sectional views of FIGS. 6(b) and 6(c) are taken from the lines A--A' and B--B', respectively of the plan view of FIG. 6(a).
Inside the top surface of a semiconductive substrate 51 of a first conductivity type are disposed a plurality of parallel, strip-like shaped source/drain regions 52 of a second conductivity type. A plurality of strip-like shaped gate electrodes 54 are formed above the source/drain regions 52 to extend perpendicularly thereto and be spaced with each other at a fixed interval, having a gate oxide film 53 between the gate electrodes 54 and the source/drain regions 52. Information is written in such manner that any impurity ion is selectively implanted in a channel region of memory cell transistors to form thereat a high doped region 55 of an impurity of the first conductivity type, so that threshold voltage is changed. The memory cell merely allows each transistor to memorize information only of 1 bit.
A memory cell for a mask ROM memorizing 2 bit information may be achieved, as shown in FIG. 5, by that a source/drain region and a gate electrode in MOS transistors have offset with each other, thereby allowing the transistors to have orientation in conductivity properties.
As shown in FIG. 5(a), on the surface of a semiconductive substrate 61 of a first conductivity type are formed impurity regions 62a (62c) and 62b (62d) of a second conductivity type constituting source/drain regions. A gate electrode 64 is disposed on the substrate between the specific two source/drain regions through a gate oxide film 63. The gate electrode 64 is adapted to overlap with one source/drain region 62a and be spaced at a predetermined interval "1" away from the other source/drain region 62b.
When using, as shown in FIG. 5(b), the region 62a as source and that 62b as the drain in the transistor constructed above, the offset region F provided between the gate electrode 64 and the drain region 62b is applied with high electric field to have a depletion layer 66, thereby causing a channel region 67 and the drain 62b to electrically communicate with each other.
In case that the region 62c is used as drain and that 62d as source as shown in FIG. 5(c), the depletion layer 66 is not formed at the offset region F, so that the source region 62d does not communicate electrically with the channel region 67.
This technique may be adopted to allow MOS transistors to have orientation in conductivity properties and be capable of exhibiting the following four states.
i) Every source and drain regions in transistors overlap with gate electrodes, thereby enabling electrical communication in both of normal and reverse directions.
ii) Only source regions overlap with gate electrodes, so that there causes electrical communication in a normal direction but not so in a reverse direction.
iii) Only drain regions overlap with gate electrodes, so that there is no electrical communication in the normal direction but is in the reverse direction.
iv) Each of source and drain regions are kept away from gate electrodes, so that there causes no electrical communication in either direction.
Accordingly, information is read out of each memory cell transistor two times in the normal and reverse directions, thereby enabling reading of 2 bit information.
The conventional NOR-type mask ROM as shown in FIG. 6(b) is so constructed that gate electrodes 54 completely overlap with the source/drain regions 52, so that the mask ROM can not be applied with a function for a memory cell transistor memorizing 2 bit information as shown in FIG. 5, thereby being hindered from developing into a larger scale device.